This invention relates to a multi-processor system with hierarchy buffer storages, and particularly to a multi-processor system of a hierarchy storage structure having a main storage and two- or more-layered hierarchy buffer storages, wherein there exists a plurality of buffer storages in each layer.
In a multi-processor system in which a plurality of processors, each of which has a buffer storage, share a main storage, it is required that the coincidence between data in the main storage and those in each of the buffer storages is guaranteed and that all of the buffer storages utilize the newest data. In U.S. Pat. No. 3,618,040 and Japanese Patent Kokoku Publication No. 12020/1974 it is disclosed that when a certain processor stores new data in its buffer storage and/or main storage, it transmits the address of the store to the other processors to invalidate the data stored in the buffer storage of the other processors and thus the coincidence between the data stored in the main storage and those stored in each of the buffer storages is guaranteed.
U.S. Pat. No. 4,056,844 discloses a memory control system having two buffer address arrays BAA-1 and BAA-2 storing identical contents as a directory of the buffer storage. In this case, when a store operation has been effected in the storage of each of the processors, it is necessary to examine by means of one of the buffer address arrays whether the data of the address transmitted by another processor is held or not. For this reason, in each of the processors, access to the buffer storage is prevented by the store operation in the other processors. The U.S. Patent mentioned above discloses that BAA-1 is used as a directory for access to the buffer storage and BAA-2 is used for invalidation process by the address transmitted by the other processor.
The U.S. Pat. No. 4,056,844 discloses that the directory of the private storage (buffer storage) contains a fetch only bit (F bit). When the F bit is in the binary "0" state, this indicates that the specified buffer storage has only one copy of a data block from the shared main storage. When the F bit is in the binary "1" state, this indicates that one of the other processors has transmitted the same data block from the shared main storage to the buffer storage at a certain point of time. According to this U.S. Patent, the processor, which has stored new data, does not transmit the store address to the other processors and in this way it is possible to reduce the hindrance of access to the buffer storage in the other processors.
All the prior art techniques described above disclose systems having a single-layered buffer storage and no system with buffer storages of two- or more-layered hierarchy is considered.